This market will resolve to “Yes” if, at any time after the creation of this market and before March 1, 2027 - 00:00 UTC, a new DRAM architecture or microarchitecture is publicly announced and demonstrated in silicon (prototype or production) that is documented to improve DRAM energy efficiency by 20% or more relative to a comparable prior-generation commercial DRAM device, and that measured improvement is reported in one or more of the resolution sources listed below.

Otherwise this market will resolve to “No.”

For the purposes of this market:

• “DRAM architecture or microarchitecture” means changes to internal memory organization, cell-array/refresh schemes, bank/subarray structure, access protocols, or other internal DRAM design changes that alter how DRAM stores or accesses data.

• Process-node-only improvements, packaging-only changes, board-level power management, interface-only speed/bandwidth increases, firmware-only power tweaks, or marketing projections/simulations without measured silicon/prototype results do not qualify.

• “Improvement of 20% or more” must be a measured, quantified improvement in energy efficiency (for example, average active energy per bit for reads/writes or energy-delay product) reported from measured silicon or prototype results (not only simulation). Claims based solely on projected or simulated gains do not qualify.

• “Comparable prior-generation commercial DRAM device” means the vendor’s immediately preceding commercially available product in the same product segment (e.g., DDR5, LPDDR5, HBM) or a widely accepted baseline where a vendor predecessor is not applicable.

• Only announcements and measured results first published after this market’s creation are eligible for resolution.